1. Field of the Invention
Embodiments of the invention relate to a semiconductor memory device. More particularly, embodiments of the invention relate to a semiconductor memory device including decoding signal generators adapted to generate decoding signals.
This application claims priority to Korean Patent Application No. 10-2006-6052, filed on Jan. 20, 2006, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
A conventional semiconductor memory device includes a memory array including memory cells (which are storage elements capable of storing data) disposed in a matrix having rows and columns. In the conventional semiconductor memory device illustrated in FIG. (FIG.) 1, word lines WLs are disposed along the rows of the matrix (i.e., in a row direction), and bit lines BLs are disposed along columns of the matrix (i.e., in a column direction). Memory cells MCs are respectively disposed at intersections of word lines WLs and bit lines BLs. That is, each memory cell MC is disposed at the intersection of a word line WL and a bit line BL. Furthermore, the conventional semiconductor memory device of FIG. 1 comprises several circuits for selecting memory cells MCs and inputting and outputting data.
FIG. 1 is a layout diagram illustrating an arrangement of circuits in a conventional semiconductor memory device. As illustrated in FIG. 1, a memory array MCARR is divided into a plurality of sub-arrays S_ARRs, and a sense amplifier area BK_SA is disposed between sub-arrays S_ARRs that are separated from one another in a bit line BL direction. Furthermore, a word line driver area BK_SWD is disposed on one side of each sub-array S_ARR such that each word line driver area BK_SWD is adjacent to a sub-array S_ARR along a word line WL direction. In addition, a junction area JNC is disposed at an area where sense amplifier area BK_SA and word line driver areas BK_SWDs would intersect if sense amplifier area BK_SA extended in the word line WL direction and word line driver areas BK_SWDs extended in the bit line BL direction.
As used herein, the “word line WL direction” (or “word line direction”) comprises any direction substantially parallel to a row of a sub-array S_ARR. Thus, every direction substantially parallel to a row of a sub-array S_ARR points in the word line WL direction. The arrow labeled WL in FIG. 1, for example, is pointing in the word line WL direction, and any other arrow parallel to and pointing in the same direction as or pointing in the opposite direction relative to one of the arrows labeled WL in FIG. 1 would also be pointing in the word line WL direction. The word line WL direction is indicated by arrows in other drawings as well.
Also, as used herein, the “bit line BL direction” (or “bit line direction”) comprises any direction substantially parallel to a column of a sub-array S_ARR. Thus, every direction substantially parallel to a column of a sub-array S_ARR points in the bit line BL direction. The arrows labeled BL in FIG. 1, for example, are each pointing in the bit line BL direction, and any other arrow parallel to either of those arrows would also be pointing in the bit line BL direction. The bit line BL direction is indicated by arrows in other drawings as well.
Bit line sense amplifiers BLSAs adapted to detect and amplify data apparent on the bit lines are disposed in sense amplifier area BK_SA. In addition, sub-word line drivers SWDs are disposed in word line driver areas BK_SWDs.
Each of the sub-word line drivers SWDs drives a word line WL in accordance with (i.e., designated by) a word line enable signal NWE<k>, which is provided from an enable signal generator NWEG<k>, a pair of signals comprising a delay decoding signal PXD<i> and inverted decoding signal PXB<i>. Delay decoding signal PXD<i> and inverted decoding signal PXB<i> are provided from a decoding driver PXDV<i>.
Decoding drivers PXDV<1>, PXDV<2> (which are called “PX drivers”) are disposed in junction area JNC. Decoding drivers PXDV<1>, PXDV<2> generate delay decoding signals PXD<1> and PXD<2> and inverted decoding signal PXB<1> and PXB<2>, which are driven in response to predecoding signals PX<1> and PX<2> provided from decoding signal generators PXG<1> and PXG<2>.
Furthermore, a predecoder 11 decodes a row address RADD provided from outside of the conventional semiconductor memory device of FIG. 1 and provides a first address signal XA<1> to decoding signal generators PXG<1> and PXG<2> and provides second address signals XA<2:8> to enable signal generators NWEG<1> to NWEG<128>.
For convenience of description, it will be assumed that the sub-word line drivers SWDs disposed in one of the word line driver areas BK_SWDs drive word lines WLs of a corresponding one of sub-array S_ARRs. The conventional semiconductor memory device of FIG. 1 comprises 256 word lines WLs for each sub-array S_ARR, and 256 sub-word line drivers SWDs are disposed in each word line driver area BK_SWD of the conventional semiconductor memory device of FIG. 1. For the purpose of clarity, sense amplifier area BK_SA, word line driver areas BK_SWDs, and junction area JNC of FIG. 1 are not drawn to scale.
In the conventional semiconductor device of FIG. 1, decoding drivers PXDV<1> and PXDV<2> are disposed in junction area JNC. Therefore, delay decoding signals PXD<1> and PXD<2> and inverted decoding signals PXB<1> and PXB<2>, which are generated by decoding drivers PXDV<1> and PXDV<2>, are connected to a relatively large number of sub-word line drivers SWDs, as is illustrated in FIG. 2. In the conventional semiconductor memory device of FIGS. 1 and 2, each of delay decoding signals PXD<1> and PXD<2> and each of inverted decoding signal PXB<1> and PXB<2> is connected to 128 sub-word line drivers SWDs disposed in the word-line driver area BK_SWD disposed to the right of junction area JNC and 128 sub-word line drivers SWDs disposed in the word-line driver area BK_SWD disposed to the left of junction area JNC. Thus, each of delay decoding signals PXD<1> and PXD<2> and each of inverted decoding signal PXB<1> and PXB<2> is connected to a total of 256 sub-word line drivers SWDs.
Because delay decoding signals PXD<1> and PXD<2> and inverted decoding signals PXB<1> and PXB<2> are connected to a relatively large number of sub-word line drivers SWD, delay decoding signals PXD<1> and PXD<2> and inverted decoding signals PXB<1> and PXB<2> are burdened with a relatively heavy load. In particular, when delay decoding signals PXD<1> and PXD<2> are driven to a high voltage level of boost voltage level VPP, the relatively heavy load caused by delay decoding signals PXB<1> and PXB<2> being connected to a relatively large number of sub-word line drivers SWDs in a semiconductor memory device may cause the overall operational speed of the semiconductor memory device to decrease.